[NSWI004] [Teachers at NSWI004] Graded 09 - Q3 clarification

[Petr Tuma]

Hello,

> in question Q3 you mention Figure 4-8 with title Linear-Address
> Translation to a 4-KByte Page using 4-Level Paging. However in Intel
> manual I found [1] Figure 4-8 is named Linear-Address Translation to
> a 4-KByte Page using IA-32e Paging. Am I using the correct manual?

> [1]
> https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf
> <https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf>
As pointed out in the initial course information, we are using the May 2020 version of the manual, titled "Intel® 64 and IA-32 Architectures Software Developer’s Manual (Version 325462-072)", available from https://software.intel.com/content/www/us/en/develop/articles/intel-sdm.html. Intel has recently released Version 325462-073, which also works, in both versions Figure 4-8 with the name "Linear-Address Translation to a 4-KByte Page using 4-Level Paging" is the right one.

Your link is to an old version of the document from September 2016, where Figure 4-8 is called "Linear-Address Translation to a 4-KByte Page using IA-32e Paging" but is actually the same figure as in the newer versions, only the name differs, so it should work for the quiz just fine.

Petr