[NSWI004] TLB refill

[Petr Tuma]

Hello Georgii,

> One more question. I did look through the assembly code and through MIPS manual and as far as I understand when we get a TLB miss CPU should go to tlb refill handler directly, but for some reason our code goes to general_exception_handler. Is that correct or do we have a problem?

There are three different TLB exceptions on the MIPS CPU, TLB Refill, TLB Invalid and TLB Modified.

- TLB Refill is called when there is no TLB entry matching the virtual address used (no entry where `VA & mask == VPN` and either `ASID == entry ASID` or `entry global`). This is the exception you should focus on in your assignments.

- TLB Invalid is called when there is a TLB entry matching the virtual address used, but the `valid` bit is zero. This is an exception that you might see when working on your assignments, in particular if you leave current ASID at zero and use the initial TLB content, which is also all zeros, so it happens to match all addresses. If you assign ASID to your threads correctly (and do not start with the zero ASID), you should not need to handle this exception I think.

- TLB Modified is called when there is a TLB entry matching the virtual address used, but the `dirty` bit is zero and the access is a write. This is intended for swapping so that the kernel can remember what pages are dirty. Since you do not have swapping, just set the dirty bit in the TLB entries to one from the start and you should never see this exception.

Only TLB Refill has its own handler. Both TLB Invalid and TLB Modified are delivered to the general exception handler and can be recognized by looking at the CP0 registers.

Petr