Virtual memory makes it possible to create a virtual view of memory by defining a mapping between virtual and physical addresses. Instructions access memory using virtual addresses that the hardware either translates to physical addresses or recognizes as untranslatable and requests the software to supply the translation.
Memory accesses used to fetch instructions and their operands and results exhibit locality of reference. A processor can keep a copy of the recently accessed instructions and data in a cache that can be accessed faster than other memory.
A cache is limited in size by factors such as access speed and chip area. A cache may be fully associative or combine a limited degree of associativity with hashing. Multiple levels of caches with different sizes and speeds are typically present to accommodate various memory access patterns.
The copy of the instructions and data in a cache must be coherent with the original. This is a problem when other devices than a processor access memory. A cache coherency protocol solves the problem by snooping on the processor bus and either invalidating or updating the cache when an access by other devices than a processor is observed.