[NSWI004] Timer enabling

[Ondřej Hrubý]

Hi there,

I am still having problems enabling the timer. I have already done following:

• Set bit 0 of Status register to 1 for enabling interrupts in general.
• Set bit 15 of Status register (interrupt mask) to 1 for enabling timer interrupt.

I have a printk call in handle_exception_general and nothing prints out on the
screen.

I've searched the MIPS manual [1] and there is written (on PDF page 139) that
ERL bit in Status register must be set to 0 in order to enable interrupts in
general. But there is also written that setting ERL=0 leaves kernel mode, and I
have found somewhere that it also changes the memory mapping layout.

When I set ERL=0, the interrupts start triggering but the cause is 2, which
means TLB exception. I guess that this is because of the changed memory mapping
which was caused by ERL=0. The TLB exception is probably generated somewhere in
handlers.S when context-switching to timer interrupt handler because I do not
get TLB exception if I set timer_interrupt_after(X) where X < (#of total program
cycles).

I am a little bit confused. Are we expected to modify these low-level things in
order to enable the timer, or are we supposed to only use the provided code?

Thanks for any suggesions in advance!

Ondřej Hrubý


[1] 
https://d3s.mff.cuni.cz/files/teaching/nswi004/download/R4000_Users_Manual_2Ed.pdf