[NSWI004] Timer enabling

[Vojtech Horky]

Hello.

Dne 07. 12. 19 v 19:15 Ondřej Hrubý napsal(a):
> I am still having problems enabling the timer. I have already done following:
> 
> • Set bit 0 of Status register to 1 for enabling interrupts in general.
> • Set bit 15 of Status register (interrupt mask) to 1 for enabling timer interrupt.
> 
> I have a printk call in handle_exception_general and nothing prints out on the
> screen.

I guess you have not available this in GitLab right? I see no such code 
in your repository.


> I've searched the MIPS manual [1] and there is written (on PDF page 139) that
> ERL bit in Status register must be set to 0 in order to enable interrupts in
> general. But there is also written that setting ERL=0 leaves kernel mode, and I
> have found somewhere that it also changes the memory mapping layout.

Looking at page 73 (Kernel Mode Operations) I do not think you 
interpreted the ERL bit correctly.


> When I set ERL=0, the interrupts start triggering but the cause is 2, which
> means TLB exception. I guess that this is because of the changed memory mapping
> which was caused by ERL=0. The TLB exception is probably generated somewhere in
> handlers.S when context-switching to timer interrupt handler because I do not
> get TLB exception if I set timer_interrupt_after(X) where X < (#of total program
> cycles).

That is weird. TLB exception should first trigger the TLB refill 
handler, currently switching MSIM to interactive mode...

For such remote (and off-line too) debugging to work, it is necessary to 
at least send dump of registers (including CP0 ones), dump of TLB and at 
least a partial trace (last few instructions).


> I am a little bit confused. Are we expected to modify these low-level things in
> order to enable the timer, or are we supposed to only use the provided code?

No, it should not be necessary. But it is necessary to properly set 
status register of newly created threads. Looking at notes to your 
solution, I see that you have not set it. Perhaps that might be the 
culprit...

BTW, status register on boot is not in state that should be kept 
forever. For example, we clear the BEV bit quite soon but other bits are 
kept unchanged...

Hope this helps,

- VH