[NSWI004] Upstream repository update

[Vojtech Horky]

Hello,

after a debugging session we realized that it might be simpler for you 
to have basic exception handling in the kernel (even though for current 
assignment you do not need any exception handling to be present). You 
may encounter exceptions when, for example, you read from TLB mapped 
memory by accident.

Now the processor would enter an endless loop without any hint to the 
outside about what is happening.

The latest commit (2777f7d68008) to the upstream repository adds an 
exception handling that stops the simulation and enters interactive 
mode. Later on you will change this code into proper exception handling 
routines.

When in interactive mode, you can check register contents to see why the 
exception occurred (e.g. cpu0 cp0d 13 gives the contents of cause register).

- VH