Resources

This page provides more detailed information about individual lectures as well as links to various resources. Students are encouraged to read selected textbook chapters and review slides before the lecture.

Lecture videos

Lecture videos are available in a shared folder on university SharePoint. Use <your-login>@cuni.cz on the log-in screen where <your-login> is the login name you use to log into the Study Information System (SIS).

Digital circuit designs

Digital circuit designs are available for some of the lectures. These are for use with the LogiSim Evolution simulator, version 3.3.0 or later (tested with version 3.4.2). See the lectures below for links to specific designs.

Lecture 1 (Mar 2, Mar 4)

Lecture 2 (Mar 9, Mar 11)

  • Computer performance
    • Execution (response) time
    • Throughput
    • Classic performance equation
    • Execution time, clocks per instruction (CPI), clock rate
    • Amdahl’s law
  • Instruction set architecture
    • For review only (self-study)
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Chapter 2, Instructions: Language of the Computer

Lecture 3 (Mar 16, Mar 18)

  • Digital circuits
    • Combinational circuits
    • Logical functions and basic gates
    • Fundamental operation: 1-bit addition
    • Simple arithmetics: n-bit addition
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Appendix B, sections B.1 to B.3, B.5
  • LogiSim: Simple adder

Lecture 4 (Mar 23, Mar 25)

  • Digital circuits
    • Simple arithmetics: subtraction
    • Sequential circuits, clock
    • Memory elements: flip-flops, registers
    • Sequential multiplication and division
  • Processor implementation
    • MIPS ISA overview
    • Single-cycle data path implementation
      • fetching instructions
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Appendix B, sections B.7, B.8
    • Chapter 4, sections 4.1, 4.2, and 4.3
  • LogiSim: Simple adder/subtractor
  • LogiSim: Simple flip-flop

Lecture 5 (Mar 30, Apr 1)

  • Processor implementation
    • Single-cycle data path implementation
      • register-register, register-immediate, load/store, conditional branch, and absolute jump instructions
    • Higher-level blocks for data path construction
      • 32-bit ALU built from 32 1-bit ALUs
      • 32-register file built from 4 8-register files
      • Simple circuits: multiplexers, decoders, sign/zero extension, zero detection
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Chapter 4, section 4.3

Lecture 6 (Apr 6, Apr 8)

  • Processor implementation
    • Single-cycle data path controller implementation
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Chapter 4, section 4.4
    • Appendix D, sections D.1 and D.2 (controller)
  • LogiSim: Single-cycle MIPS data path implementation
    • The Instruction Memory (ROM) contains the following Bubble Sort program.
  • Bubble Sort
    • Sorts 16 integers starting at address 0x80.
    • Hand-written assembly version (bubble_sort.S) with a memory dump from QtMIPS (bubble_sort.dump) and a memory dump that can be loaded into Instruction Memory in LogiSim (bubble_sort.raw).
    • Memory dump with sample data that can be loaded into the Data Memory in LogiSim (bubble_sort-data.raw).
    • C version (c_bubble_sort.c) with compiler-produced assembly (c_bubble_sort-O2.s) and objdump-produced dissassembly (c_bubble_sort-O2.objdump). Compiled using GCC at optimization level -O2. For illustration purposes only – the current implementation of the processor is not able to execute the GCC-generated code, but adding support for the few missing instructions should be relatively straightforward.
  • QtMIPS, a MIPS simulator developed at CTU
    • Allows simulating different variants of MIPS processors, including cache
    • Provides integrated editor that allows editing and compiling MIPS assembly code
    • To simulate single-cycle data path, use the following settings
      • Basic tab: no pipeline, no cache preset
      • Core tab: no delay slot

Lecture 7 (Apr 13, Apr 15)

  • Processor implementation
    • Implementing multi-cycle data path
  • Hennessy & Patterson, Computer Organization and Design (3rd ed.)
    • Chapter 5, section 5.5 (multicycle datapath)

Lecture 8 (Apr 20, Apr 22)

  • Processor implementation
    • Implementing controller for the multi-cycle data path
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Appendix D, sections D.3 and D.4 (controller)
  • Hennessy & Patterson, Computer Organization and Design (3rd ed.)
    • Chapter 5, section 5.5 (multicycle datapath)
  • LogiSim: Multi-cycle MIPS data path implementation
    • First 128 bytes of RAM are shadowed by ROM which contains the Bubble Sort program

Lecture 9 (Apr 27, Apr 29)

Lecture 10 (May 4, May 6)

  • Issues in instruction pipelining
    • Pipeline hazards, branch prediction, exceptions
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Chapter 4, sections 4.7 to 4.19
  • LogiSim: Pipelined MIPS data path implementation
    • Note that the Bubble Sort program needs to be modified for each variant of the pipeline, because the pipeline lacks the hazard detection unit (making it a true Microprocessor without Interlocked Pipeline Stages)
    • Each variant has its own instruction memory containing the correct version of the Bubble Sort program
  • Bubble Sort for the pipelined data path
    • Different variants of the Bubble Sort program for different pipeline variants

Lecture 11 (May 11, May 13)

  • Super-scalar pipelines
    • Static multiple issue (in-order super-scalar) pipeline
    • Dynamic multiple issue (out-of-order super-scalar) pipeline
    • Speculative execution, exception handling
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Chapter 4, sections 4.10, 4.11, 4.14, and 4.15

Lecture 12 (May 18, May 20)

  • Memory technology and memory hierarchy
    • Static and dynamic memory technology
    • Memory hierarchy concepts
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Chapter 5, sections 5.1, 5.2, and 5.3
  • LogiSim: Static RAM model
    • The static RAM circuit (memory_static_8x8bit) shows a row decoder and the organization of a 8x8 memory cell matrix, down to S-R flip-flops made of NOR gates.
    • The memory cells use a controlled buffer to avoid driving the bit lines when not enabled by a word line, which allows connecting the cell outputs to a shared bit line.
  • Circuit: DRAM cell example
    • Logical 0 corresponds to 0 Volts, logical 1 corresponds to 1 Volt
    • Bit information (logical 0 or 1) is stored as charge in a capacitor (Cs)
    • To read the value, the bit line (represented by capacitor Cbl) is precharged to 0.5 Volts (value in the middle between logical 0 and 1)
    • When reading the information stored in Cs, we are looking for an upwards or downwards swing in voltage (or alternatively, in current) resulting from charge equalization between Cs and Cbl.
    • The voltage (current) swing is picked up and aplified by a sense amplifier (not shown in the circuit)

Lecture 13 (May 25, May 27)

  • Cache architectures
    • Direct-mapped cache architecture
    • Set-associative cache architecture
    • Fully associative cache architecture
    • Architectural parameters (ABC) and their impact on cache performance
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Chapter 5, sections 5.4, and 5.8
  • LogiSim: Cache models
    • Includes direct-mapped (64 KiB), 4-way associative (64 KiB) and fully-associative (512 B) cache models for 32-bit addresses.
    • All cache models use conceptually similar components to better demonstrate the commonality and the differences in their internal architecture.
    • The cache models support either an update or a replacement of a cache line on write (think of replacement as setting the entire cache line to zero before storing the word being written).

Lecture 14 (Jun 1, Jun 3)

  • Cache architectures
    • 3C model of cache misses
    • Write-through (WT) and write-back (WB) caches
    • Handling hits and misses in WT and WB caches
    • Multi-level cache organization
  • Cache coherence
    • Cache coherence problem in multi-core and multi-processor system
    • Cache coherence protocols for WT and WB caches
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Chapter 5, sections 5.9, 5.10, 5.12 (part related to cache coherence), 5.14, 5.15, and 5.16