This page provides more detailed information about individual lectures as well as links to various resources. Students are encouraged to read selected textbook chapters and review slides before the lecture.

Lecture 1 (Feb 18, 2025)

  • Agenda
  • Introduction
    • What’s below your program
    • Abstraction as a tool
  • Hennessy & Patterson, Computer Organization and Design
    • Chapter 1, Computer Abstractions and Technology

Lecture 2 (Feb 25, 2025)

  • Computer performance
    • Execution (response) time
    • Throughput
    • Classic performance equation
    • Execution time, clocks per instruction (CPI), clock rate
    • Amdahl’s law
  • Hennessy & Patterson, Computer Organization and Design
    • Chapter 1, Computer Abstractions and Technology

Lecture 3 (Mar 5, 2025)

Lecture 4 (Mar 11, 2025)

  • Digital circuits
    • Sequential circuits, clock
    • Memory elements: flip-flops, registers
    • Sequential multiplication and division (overview)
  • Processor implementation (if time permits)
    • RISC-V ISA overview
    • Single-cycle data path implementation
      • fetching instructions
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Appendix A, sections B.7, B.8
    • Chapter 4, sections 4.1, 4.2, and 4.3
  • LogiSim: Simple flip-flop

Lecture 5 (Mar 18, 2025)

  • Processor implementation
    • Single-cycle data path implementation
      • register-register, register-immediate instructions
      • load/store instructions
      • conditional branch instruction
    • Higher-level blocks for data path construction
      • 32-bit ALU built from 32 1-bit ALUs
      • 32-register file built from 4 8-register files
      • Simple circuits: multiplexers, decoders, sign/zero extension, zero detection
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Chapter 4, section 4.3
  • Hennessy & Patterson, Computer Organization and Design: RISC-V Edition (2nd ed.)
    • Chapter 4, section 4.3
  • LogiSim: Single-cycle RISC-V data path implementation
    • Uses a 6-function ALU with support for signed and unsigned comparison.
    • Contains also libraries of generic and RISC-V-specific components.

Lecture 6 (Mar 25, 2025)

  • Processor implementation
    • Single-cycle data path controller implementation
    • Overview of multi-cycle data path implementation (without controller)
  • Hennessy & Patterson, Computer Organization and Design: RISC-V Edition (2nd ed.)
    • Chapter 4, section 4.4 (single-cycle datapath)
    • Chapter 4, section 4.5 (multi-cycle datapath)
    • Appendix C, sections C.1 and C.2 (combinational controller)
  • LogiSim: Single-cycle RISC-V data path implementation
    • The Instruction Memory (ROM) contains the following Bubble Sort program.
  • Bubble Sort
    • Sorts 16 integers starting at address 0x80.
    • Hand-written assembly version (bubble_sort-riscv.S) with an objdump-produced diassassembly (with and without instruction aliases) and memory dump that can be loaded into Instruction Memory in LogiSim (bubble_sort-riscv.raw).
    • Memory dump with sample data that can be loaded into the Data Memory in LogiSim (bubble_sort-data.raw).
    • C version (c_bubble_sort.c) with compiler-produced assembly (c_bubble_sort-O2-riscv.s) and objdump-produced dissassembly (c_bubble_sort-O2-riscv.objdump). Compiled using GCC at optimization level -O2. For illustration purposes – the current implementation of the processor does not support all instructions used in the GCC-generated code, but adding support for the few missing instructions should be relatively straightforward.

Lecture 7 (Apr 1, 2025)

  • Processor implementation
    • Multi-cycle data path implementation
    • Microcode controller for the multi-cycle data path
    • Wired controller for the multi-cycle data path
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Appendix D, sections D.3 and D.4 (controller)
  • Hennessy & Patterson, Computer Organization and Design: RISC-V Edition (2nd ed.)
    • Chapter 4, section 4.5 (multi-cycle data path)
    • Appendix C, sections C.3, C.4 and C.5 (controller)
  • LogiSim: Multi-cycle RISC-V data path implementation
    • First 128 bytes of RAM are shadowed by ROM which contains the Bubble Sort program

Lecture 8 (Apr 8, 2025)

  • Improving performance through pipelining
    • Implementing pipelined data path and control
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Chapter 4, sections 4.5 and 4.6
  • Hennessy & Patterson, Computer Organization and Design: RISC-V Edition (2nd ed.)
    • Chapter 4, sections 4.6 and 4.7

Lecture 9 (Apr 15, 2025)

  • Improving performance through pipelining
    • Pipeline hazards (structural, data and control)
  • Hennessy & Patterson, Computer Organization and Design (5th ed.)
    • Chapter 4, sections 4.6 to 4.8
  • LogiSim: Pipelined RISC-V data path implementation
    • Note that the Bubble Sort program needs to be modified for each variant of the pipeline, depending on the kind of hazards handled by a particular variant.
    • Each variant has its own instruction memory containing the correct version of the Bubble Sort program
  • Bubble Sort for the pipelined data path
    • Different variants of the Bubble Sort program for different pipeline variants