Computer Architecture

This page provides more detailed information about individual lectures as well as links to various resources. Students are encouraged to read selected textbook chapters and review slides before the lecture.

Lecture 1 (Feb 19, 2026)

• Agenda
• Introduction
  • What’s below your program
  • Abstraction as a tool
• Hennessy & Patterson, Computer Organization and Design
  • Chapter 1, Computer Abstractions and Technology
• Extras
  • How ASML took over the chipmaking chessboard
  • The World’s Most Important Machine

Lecture 2 (Feb 26, 2026)

• Computer performance
  • Execution (response) time
  • Throughput
  • Classic performance equation
  • Execution time, clocks per instruction (CPI), clock rate
  • Amdahl’s law
• Hennessy & Patterson, Computer Organization and Design
  • Chapter 1, Computer Abstractions and Technology

Lecture 3 (Mar 5, 2026)

• Digital circuits
  • Combinational circuits
  • Logical functions and basic gates
  • Fundamental operation: 1-bit addition
  • Simple arithmetics: n-bit addition, subtraction
• Hennessy & Patterson, Computer Organization and Design (5th ed.)
  • Appendix B, sections B.1 to B.3, B.5
• Gates and logic families in Circuit Simulator
  • basic gates made of manually operated switches
  • observe the differences in current at the ground terminal
  • RTL Inverter, NAND Gate
  • TTL Inverter, NAND Gate
  • NMOS Inverter, NAND Gate
  • CMOS Inverter, NAND Gate
• LogiSim: Simple adder
• LogiSim: Simple adder/subtractor

Lecture 4 (Mar 12, 2026)

• Digital circuits
  • Sequential circuits, clock
  • Memory elements: flip-flops, registers
  • Sequential multiplication and division (overview)
• Processor implementation (if time permits)
  • RISC-V ISA overview
  • Single-cycle data path implementation
    • fetching instructions
• Hennessy & Patterson, Computer Organization and Design (5th ed.)
  • Appendix A, sections B.7, B.8
  • Chapter 4, sections 4.1, 4.2, and 4.3
• LogiSim: Simple flip-flop

Lecture 5 (Mar 19, 2026)

• Processor implementation
  • Single-cycle data path implementation
    • register-register, register-immediate instructions
    • load/store instructions
    • conditional branch instruction
  • Higher-level blocks for data path construction
    • 32-bit ALU built from 32 1-bit ALUs
    • 32-register file built from 4 8-register files
    • Simple circuits: multiplexers, decoders, sign/zero extension, zero detection
• Hennessy & Patterson, Computer Organization and Design (5th ed.)
  • Chapter 4, section 4.3
• Hennessy & Patterson, Computer Organization and Design: RISC-V Edition (2nd ed.)
  • Chapter 4, section 4.3
• LogiSim: Single-cycle RISC-V data path implementation
  • Uses a 6-function ALU with support for signed and unsigned comparison.
  • Contains also libraries of generic and RISC-V-specific components.

Lecture 6 (Mar 26, 2026)

Lecture 7 (Apr 2, 2026)

Lecture 8 (Apr 9, 2026)

Lecture 9 (Apr 16, 2026)

Lecture 10 (Apr 23, 2026)

Lecture 11 (Apr 30, 2026)

Lecture 12 (May 7, 2026)

Lecture 13 (May 14, 2026)

Lecture 14 (May 21, 2026)