Note that the Bubble Sort program needs to be modified for each variant of the pipeline, because
the pipeline lacks the hazard unit (which makes it truly a Microprocessor without Interlocked Pipeline Stages)
Each variant has its own instruction memory containing the correct version of the Bubble Sort program
Different variants of the Bubble Sort program for different pipeline variants
Also contains a C version compiled by GCC at different optimization levels into assembly and object files
(the current implementation is not able to execute the GCC-generated code, but adding support for the few
missing instructions should be relatively straightforward–at least in the single-cycle datapath).
Logical 0 corresponds to 0 Volts, logical 1 corresponds to 1 Volt
Bit information (logical 0 or 1) is stored as charge in a capacitor (Cs)
To read the value, the bit line (represented by capacitor Cbl) is precharged
to 0.5 Volts (value in the middle between logical 0 and 1)
When reading the information stored in Cs, we are looking for
an upwards or downwards swing in voltage (or alternatively, in current)
resulting from charge equalization between Cs and Cbl.
The voltage (current) swing is picked up and aplified by a sense amplifier
(not shown in the circuit)
Static RAM circuit (memory_static_8x8bit), shows row decoder and the
organization of a 8x8 memory cell matrix, down to S-R flip-flops made of NOR gates
Direct-mapped cache circuit (cache_direct_mapped_64k), shows organization
of a 64 KiB direct-mapped cache (64 B cache lines) for 32-bit address space.
The memory cell in the static RAM circuit (memory_static_8x8bit) now uses
a controlled buffer to avoid driving the bit lines when not enabled by a
word line. This avoids electrical issues where multiple cells were driving
the bit line with opposite values.
Includes direct-mapped (64 KiB), 4-way associative (64 KiB) and
fully-associative (512 B) cache models for 32-bit addresses. All cache
models use conceptually similar components to better demonstrate the commonality
and differences in their internal architecture.
The models of static memory and cache architectures have been split into separate files.
The cache models now support either update or replacement of a cache line.
The cache models have been refactored to look similar, the only differences
being the top-level architecture and the internals of the data storage components.